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RT Book, Whole SR Print DC OPAC T1 Hierarchical modeling for VLSI circuit testing / by Debashis Bhattacharya, John P. Hayes T2 The Kluwer international series in engineering and computer science A1 Bhattacharya, Debashis, 1961- A1 Hayes, John P. (John Patrick), 1944- YR 1990 FD c1990 SP x, 159 p. K1 Integrated circuits -- Very large scale integration -- Testing K1 Integrated circuits -- Very large scale integration -- Computer simulation PB Kluwer Academic Publishers PP Boston SN 079239058X LA English (英語) CL LCC:TK7874 CL DC20:621.39/5/0287 NO Includes bibliographical references (p. [149]-155) NO 書誌ID=B000086827; NCID=BA09998982; LK [OPAC]https://lib.pu-toyama.ac.jp/opac/opac_link/bibid/B000086827 OL 30