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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings / edited by Johan Vounckx, Nadine Azemard, Philippe Maurine
(Theoretical Computer Science and General Issues. ISSN:25122029 ; 4148)

データ種別	電子ブック
版	1st ed. 2006.
出版者	(Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer)
出版年	2006
大きさ	XVI, 677 p : online resource
著者標目	Vounckx, Johan editor Azemard, Nadine editor Maurine, Philippe editor SpringerLink (Online service)

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URL	巻　次	配架場所	請求記号	登録番号	コメント	刷　年	状　態	利用注記	ISBN	予約	請求メモ
URL		射水-電子	007	EB0004040	Computer Scinece R0 2005-6,2022-3				9783540390978

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一般注記	Session 1 – High-Level Design -- Session 2 – Power Estimation / Modeling -- Session 3 – Memory and Register Files -- Session 4 – Low-Power Digital Circuits -- Session 5 – Busses and Interconnects -- Session 6 – Low Power Techniques -- Session 7 – Applications and SoC Design -- Session 8 – Modeling -- Session 9 – Digital Circuits -- Session 10 – Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session Welcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript HTTP:URL=https://doi.org/10.1007/11847083
件　名	LCSH:Computer science LCSH:Logic design LCSH:Microprocessors LCSH:Computer architecture LCSH:Electronic digital computers -- Evaluation 全ての件名で検索 LCSH:Computer arithmetic and logic units LCSH:Computer storage devices LCSH:Memory management (Computer science) FREE:Theory of Computation FREE:Logic Design FREE:Processor Architectures FREE:System Performance and Evaluation FREE:Arithmetic and Logic Structures FREE:Computer Memory Structure
分　類	LCC:QA75.5-76.95 DC23:004.0151
書誌ID	EB00003428
ISBN	9783540390978