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Guessing Random Additive Noise Decoding : A Hardware Perspective / by Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
| データ種別 | 電子ブック |
|---|---|
| 版 | 1st ed. 2023. |
| 出版者 | (Cham : Springer Nature Switzerland : Imprint: Springer) |
| 出版年 | 2023 |
| 大きさ | XIV, 151 p. 114 illus., 101 illus. in color : online resource |
| 著者標目 | *Abbas, Syed Mohsin author Jalaleddine, Marwan author Gross, Warren J author SpringerLink (Online service) |
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| 一般注記 | Guessing Random Additive Noise Decoding (GRAND) -- Hardware Architecture for GRAND with ABandonment (GRANDAB) -- Hardware Architecture for Ordered Reliability Bits GRAND (ORBGRAND) -- Hardware Architecture for List GRAND (LGRAND) -- Hardware Architecture for GRAND Markov Order (GRAND-MO) -- Hardware Architecture for Fading-GRAND -- A survey of recent GRAND variants This book gives a detailed overview of a universal Maximum Likelihood (ML) decoding technique, known as Guessing Random Additive Noise Decoding (GRAND), has been introduced for short-length and high-rate linear block codes. The interest in short channel codes and the corresponding ML decoding algorithms has recently been reignited in both industry and academia due to emergence of applications with strict reliability and ultra-low latency requirements . A few of these applications include Machine-to-Machine (M2M) communication, augmented and virtual Reality, Intelligent Transportation Systems (ITS), the Internet of Things (IoTs), and Ultra-Reliable and Low Latency Communications (URLLC), which is an important use case for the 5G-NR standard. GRAND features both soft-input and hard-input variants. Moreover, there are traditional GRAND variants that can be used with any communication channel, and specialized GRAND variants that are developed for a specific communication channel. This book presents a detailed overview of these GRAND variants and their hardware architectures. The book is structured into four parts. Part 1 introduces linear block codes and the GRAND algorithm. Part 2 discusses the hardware architecture for traditional GRAND variants that can be applied to any underlying communication channel. Part 3 describes the hardware architectures for specialized GRAND variants developed for specific communication channels. Lastly, Part 4 provides an overview of recently proposed GRAND variants and their unique applications. This book is ideal for researchers or engineers looking to implement high-throughput and energy-efficient hardware for GRAND, as well as seasoned academics and graduate students interested in the topic of VLSI hardware architectures. Additionally, it can serve as reading material in graduate courses covering modern error correcting codes and Maximum Likelihood decoding for short codes HTTP:URL=https://doi.org/10.1007/978-3-031-31663-0 |
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| 件 名 | LCSH:Coding theory LCSH:Information theory LCSH:Telecommunication LCSH:Logic design LCSH:Computer arithmetic and logic units FREE:Coding and Information Theory FREE:Communications Engineering, Networks FREE:Logic Design FREE:Arithmetic and Logic Structures |
| 分 類 | LCC:QA268 LCC:Q350-390 DC23:003.54 |
| 書誌ID | EB00002314 |
| ISBN | 9783031316630 |
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