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Formal Verification of Floating-Point Hardware Design : A Mathematical Approach / by David M. Russinoff
| データ種別 | 電子ブック |
|---|---|
| 版 | 2nd ed. 2022. |
| 出版者 | (Cham : Springer International Publishing : Imprint: Springer) |
| 出版年 | 2022 |
| 大きさ | XXVIII, 436 p. 40 illus : online resource |
| 著者標目 | *Russinoff, David M author SpringerLink (Online service) |
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| 一般注記 | Part I - Register-Transfer Logic -- Basic Arithmetic Functions -- Bit Vectors -- Logical Operations -- Part II - Floating-Point Arithmetic -- Floating-Point Numbers -- Floating-Point Formats -- Rounding -- IEEE-Compliant Square Root -- Part III - Implementation of Elementary Operations -- Addition -- Multiplication -- SRT Division and Square Root -- FMA-Based Division -- Part IV - Comparative Architectures: SSE, x87, and Arm -- SSE Floating-Point Instructions -- x87 Instructions -- Arm Floating-Point -- Instructions -- Part V - Formal Verification of RTL Designs -- The RAC Modeling Language -- Double-Precision Multiplication and Scaling -- Double-Precision Addition and FMA -- Multi-Precision Radix-8 SRT Division -- 64-bit Integer Division -- Multi-Precision Radix-4 SRT Square Root -- Multi-Precision Radix-2 SRT Division -- Fused Multiply-Add of a Graphics Processor This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I—III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V HTTP:URL=https://doi.org/10.1007/978-3-030-87181-9 |
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| 件 名 | LCSH:Computer arithmetic and logic units LCSH:Computers LCSH:Microprocessors LCSH:Computer architecture LCSH:Electronic circuit design FREE:Arithmetic and Logic Structures FREE:Hardware Performance and Reliability FREE:Processor Architectures FREE:Electronics Design and Verification FREE:Computer Hardware |
| 分 類 | LCC:QA76.9.C62 DC23:004.01513 |
| 書誌ID | EB00001730 |
| ISBN | 9783030871819 |
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