OPAC

検索結果一覧に戻る

Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design : A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach / by Xiaowei Li, Guihai Yan, Cheng Liu

データ種別	電子ブック
版	1st ed. 2023.
出版者	(Singapore : Springer Nature Singapore : Imprint: Springer)
出版年	2023
大きさ	XVIII, 304 p. 1 illus : online resource
著者標目	*Li, Xiaowei author Yan, Guihai author Liu, Cheng author SpringerLink (Online service)

所蔵情報を非表示

URL	巻　次	配架場所	請求記号	登録番号	コメント	刷　年	状　態	利用注記	ISBN	予約	請求メモ
URL		射水-電子	007	EB0002116	Computer Scinece R0 2005-6,2022-3				9789811985515

書誌詳細を非表示

一般注記	Chapter 1: Introduction -- Chapter 2: Fault-tolerant general circuits with 3S -- Chapter 3: Fault-tolerant general purposed processors with 3S -- Chapter 4: Fault-tolerant network-on-chip with 3S -- Chapter 5: Fault-tolerant deep learning processors with 3S -- Chapter 6: Conclusion With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs. HTTP:URL=https://doi.org/10.1007/978-981-19-8551-5
件　名	LCSH:Computers LCSH:Microprocessors LCSH:Computer architecture FREE:Hardware Performance and Reliability FREE:Computer Hardware FREE:Processor Architectures
分　類	LCC:TK7885-7895 LCC:TA169-169.3 DC23:004.24
書誌ID	EB00001504
ISBN	9789811985515