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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings / edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest
(Programming and Software Engineering. ISSN:29459168 ; 3728)
| データ種別 | 電子ブック |
|---|---|
| 版 | 1st ed. 2005. |
| 出版者 | (Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer) |
| 出版年 | 2005 |
| 大きさ | XVI, 756 p : online resource |
| 著者標目 | Paliouras, Vassilis editor Vounckx, Johan editor Verkest, Diederik editor SpringerLink (Online service) |
書誌詳細を非表示
| 一般注記 | Session 1: Low-Power Processors -- Session 2: Code Optimization for Low-Power -- Session 3: High-Level Design -- Session 4: Telecommunications and Signal Processing -- Session 5: Low-Power Circuits -- Session 6: System-on-Chip Design -- Session 7: Busses and Interconnections -- Session 8: Modeling -- Session 9: Design Automation -- Session 10: Low-Power Techniques -- Session 11: Memory and Register Files -- Poster Session 1: Applications -- Poster Session 2: Digital Circuits -- Poster Session 3: Analog and Physical Design -- Special Session: Digital Hearing Aids: Challenges and Solutions for Ultra Low Power -- Invited Talks Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on “Traveling the Wild Frontier of Ulta Low-Power Design”, Dr. Sung Bae Park, S- sung, gave a presentation on “DVL (Deep Low Voltage): Circuits and Devices”, Prof HTTP:URL=https://doi.org/10.1007/11556930 |
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| 件 名 | LCSH:Logic design LCSH:Computers LCSH:Microprocessors LCSH:Computer architecture LCSH:Computer arithmetic and logic units LCSH:Computer-aided engineering LCSH:Electrical engineering FREE:Logic Design FREE:Hardware Performance and Reliability FREE:Processor Architectures FREE:Arithmetic and Logic Structures FREE:Computer-Aided Engineering (CAD, CAE) and Design FREE:Electrical and Electronic Engineering |
| 分 類 | LCC:QA76.9.L63 LCC:TK7888.4 DC23:621.395 |
| 書誌ID | EB00001439 |
| ISBN | 9783540320807 |
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